Low Power VLSI Circuit Design home work need answer now
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ELEG-548: Low Power VLSI Circuit Design, Spring 2020, Homework #3
1.(15’) A 3-input NOR gate is shown in Figure 1. Assume “1”-probabilities of 3 inputs are:
p(A)=0.5, p(B)=0.5, p(C)=0.5.
1). Use equation to find out the “1”-probability of output node p(Out)=?
2). Use equation to find the switching probability of Psw(out) for output node.
3). Now assume there are following spatiotemporal correlations among input signals,
i). Every “1” applied to A is immediately followed by “0”,
ii). CB
Given the above spatiotemporal correlations, use switching table (as shown in Table 1) to find out
the switching probability Psw(out) of the NOR gate. Compared to non-correlated case, is the output
switching probability increased or decreased?
Figure 1. CMOS NOR3 gate
Table 1: Switching table of 3-input NAND gate with correlated input signals
A B C Out Switching?
2.(15’) Kernel extraction targeting low power: For the implementation of following two functions:
F1=XꞏA+XꞏBꞏCꞏD
F2= YꞏZꞏA+YꞏZꞏBꞏCꞏD
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Assume all the input signals are random. That is, the 1-probabilities of all input signals are:
p(A)=p(B)=p(C)=p(D)=p(X)=p(Y)=p(Z)=0.5
(1). Implement both logic functions (F1 and F2) directly without kernel extraction. Sketch the gate
level diagram of the circuit.
(2). Use kernel extraction technique to re-implement the circuit, sketch the gate level diagram after
kernel extraction. Identify the kernel(s) and co-kernels of your implementation.
(3). Compare the literal counts for circuits before and after kernel implementation. How many
literal count savings do you get by kernel implementation? (Note: You also need to consider the
literal count for implementing the kernel.) Use equation we gave in the lecture to calculate the
literal count saving after kernel extraction. Is this prediction result in good agreement with your
implementation?
(4). Assume unit gate input/output capacitance. That is, for each input and output of any logic gate,
Cin=Cout=1pF. The power and frequency of the circuit are Vdd=5V and fclk=2XY MHz (where “XY”
are the last 2 digits of your student ID. For example, if your student ID is 1234567, then
fclk=267MHz) separately. Use the equation we gave in the lecture to calculate the total power
savings after kernel extraction. Does kernel extraction save power in this case?
3.(5’) Does glitch/hazard consume power? The following circuit (Figure 2) consists of 7 two-input
adder units. It implements the sum of 8 input numbers, but may cause lots of glitches/hazards.
Assume you can only use two-input adder units, try to revise the circuit architecture to reduce the
glitches/hazards so that the power consumption can be reduced (You still need to maintain the
same function for final output).
Figure 2. Block diagram of adder circuit
4. (15’) Assume implementations of two functions F1 and F2 are shown in Figure 3. Assume the
“1”-probabilities of input signals in both circuits are:
p(a)=p(c)=0.8, p(b)=0.01.
(1). List the logic functions of F1 and F2. Are they equivalent to each other? Please use Boolean
logic transformation to verify your conclusion.
(2). Find out the gate counts for both implementations. If small area is concerned in circuit design,
which implementation would you prefer?
(3). Are there any signal correlations in both circuits? Find out the 1-probabilities of all nodes for
both implementations, and mark them in
the figure.
(4). Find out the switching activities (Asw) of all nodes for both implementations, and mark them in
the figure.
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(5). Assume Vdd=5V, and working frequencies of both circuits are f=100MHz. The input and
output capacitances for all the gates are equal, and for each gate:
Cin=Cout=1pF.
Find out the power difference between implementations F1 and F2. (Note: For nodes d, e and g,
C(d)=C(e)=C(g)=6.5pF due to the output capacitance of previous gate and input capacitance of
next gate. For input capacitance of inverter, C(b)=1pF)
(6). Based on the result in step (5), if low power is preferred in circuit design, which
implementation (F1 or F2) would you choose?
(a). Implementation F1 (b). Implementation F2
Figure 3. Comparison of two functions F1 and F2
5. (15’) A State Transition Graph (STG) for a sequential circuit is shown in Figure 4. We need to
assign the states for four states S1, S2, S3 and S4 with two state registers.
Figure 4. State transition graph (STG) of a sequential circuit
1). Assume all primary inputs patterns (AB=00, 01, 10, 11) are equally probable. Based on STG,
find out conditional transition probabilities for all the transitions, and
mark them in the STG.
2). Assume the state probabilities of states are:
P(S1)=2/10, P(S2)=5/10, P(S3)=2/10, P(S4)=1/10.
Find the absolute transition probabilities Paij for all transitions between states Si and Sj (i≠j), and
mark them in the STG.
3). Based on the results, find the weights Wij for all the transitions between states Si and Sj (i≠j).
4). Based on the weighted STG, can you find out a low power state assignment for the above
sequential circuit with minimum power cost function (Fc) value? Please clearly show how you
achieve the low power state assignment step by step. Please show your state assignment matrix,
and clearly mark the state assignment for each state (S1=? S2=? S3=? S4=?).
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5). For your low power state assignment, find out the power cost function value Fc=?
6. (20’) A comparator circuit is shown in Figure 5. R1~R9 are pipeline registers. It takes six n-bit
inputs A, B, C, D, E, F:
A=An-1An-2…A0, B=Bn-1Bn-2…B0, C=Cn-1Cn-2…C0,
D=Dn-1Dn-2…D0, E=En-1En-2…E0, F=Fn-1Fn-2…F0,
The circuit first computes A+B+C and D+E+F, then compare the results.
If (A+B+C)≥(D+E+F), then f=1,
If (A+B+C)<(D+E+F), then f=0.
(1). This circuit can be revised to implement type-2 logic shut-down technique to save power. The
MSBs (Most Significant Bits) of six inputs (i.e. An-1, Bn-1, Cn-1, Dn-1, En-1, Fn-1,) can be used to
construct predictor functions. Derive the “1”-predictor function g1 and “0”-predictor function g2
for the type-2 logic shut-down implementation.
(2). Re-plot the circuit separately to show how logic shut-down technique is implemented. You
need to show clearly how g1 and g2 are connected in the circuit. (Hint: You may need to add LE
(load_enable) for some registers.)
(3). Assume the “1”-probabilities of MSBs of four inputs are:
p(An-1)=p(Bn-1)=p(Cn-1)=0.6, p(Dn-1)=p(En-1)=p(Fn-1)=0.4.
All other input bits are random. Assume the power consumption of the circuit in shut-down mode
can be neglected. What is the maximum percentage power savings you can achieve by this type-2
logic shut-down technique?
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Figure 5. A circuit to implement logic shut-down technique
7.(15’) Gated clock for low power: The State Transition Graph (STG) of a sequential circuit is
shown in Figure 6. The primary inputs are a and b, the state registers are S1S2. The state
assignments for four states Sm0~Sm2 are:
Sm0: S1S2=00, Sm1: S1S2=01, Sm2: S1S2=10, Sm3: S1S2=11.
Figure 6. State transition graph of a sequential circuit
(1). Find all the self-loops in the STG. For each self-loop, list the corresponding ab value and S1S2
value.
(2). From the results in (1), construct Karnaugh map for the gated-clock activation function Fa so
that when Fa=1, the clock signal will be “frozen”. Please fill the Karnaugh map in Figure 7 as
below.
Figure 7. Karnaugh map for gated clock activation function Fa
(3). Based on the Karnaugh map, find out the gated-clock activation function Fa. Implement it with
minimum area overhead (i.e. minimum literal count) but without abandoning any case in Karnaugh
map.
(4). Based on above derived gated-clock activation function Fa and original clock signal (“clk”),
how would you implement gated-clock signal (“gated_clk”)? Draw the gate level implementation
of “gated_clk” (draw your circuit clearly), and write the logic expression of “gated_clk”. (Note:
Your implementation should only uses clk, a, b, S1 and S2 as inputs.)
Due day: 04/16/2020 (Thursday) in class.