EE543 Introduction to Digital Systems1
LABORATORY 4
Fault Detection In Digital Logic
OBJECTIVE:
This laboratory is designed to challenge the student’s analytical skills and practical knowledge of digital
systems. The student will be asked to detect some common errors and faults found in actual logic systems.
Such detection and correction of faults is commonly referred to as troubleshooting. At the completion of the
lab you should have the ability to find and correct faults or wiring errors in simple digital logic circuits.
EQUIPMENT REQUIRED:
Global Specialties Design and Prototyping PB-505
Wire Leads
1 Logic Probe
4 7400 TTL Integrated Circuit chips
PROCEDURE:
The circuit you will build and diagnose is a straight-forward implementation of an Excess-3 (XS-3) to Binary
Coded Decimal (BCD) converter. To display the result, you will use the 7 SEGMENT DISPLAY portion of
the PB-505. This display will take the BCD input and will convert that codeword (the input) to another
codeword (the output) so that it will light the correct segments on a seven-segment display device. Our
circuit then has the effect of providing us with an Excess-3 coded decimal digit display.
You may also want to run the D, C, B, A outputs of your circuit to individual LEDs on the LOGIC MONITOR
for trouble shooting purposes.
Diagnostic Tips
Advance planning is the key to rapid location and correction of any faults or wiring mistakes. You must have
a good understanding of what the circuit does so that you do not mistake any correct results as errors.
PRE-LAB
1. Research what an excess-3 code is and describe what you find in your prelab.
2. An Excess-3 to BCD circuit is given in Figure 1. Note that, there are different stages leading up to
this final circuit design. Verify the circuit design in Figure 1 by;
a. developing a full truth table for the circuit. A full truth table includes all the intermediate
logic values (i.e. a column for each gate output. Make sure your truth table indicates the
intermediate logic results as this will help in the debug process.
b. For each output D, C, B and A, develop a k-map.
c.
From each K-map, derive the simplified Boolean expressions in the SOP form.
d. Since only NAND gates were used in the circuit design, you will need to employ the use of
De Morgan’s theorem to convert the Boolean expressions into a form representing only
NAND gates.
Last Update: 1/24/2020, 3:04 PM
EE543 Introduction to Digital Systems
2
LAB
1. Explore the 7 SEGMENT DISPLAY area of the PB-505. Document what occurs when you connect
each of the inputs to a logic switch and try different input combinations but do not spend too much
time doing so.
2. Wire your circuit according to the attached wiring list.
3. Test your circuit to verify that it performs according to the truth table you developed for PRELAB
When first wired you may have made mistakes in that wiring which will cause the results not to
match what your truth table indicates that it should be. If there are any errors in your circuit’s results
you will need to “troubleshoot” your circuit (i.e. find and correct the miswiring or logic faults) until the
circuit works as it should.
If there is a fault detected follow the following checks.
•
Check power to all ICs.
•
Document the symptoms.
•
Ensure that the proper ICs are used. This means verifying the correct chips are being used by their
part numbers as well as making sure that you have not mistakenly wired one chip as another (i.e.
wiring chip 3 with chip 2’s connections) since this can happen even with individual connections.
•
Verify that you have wired the circuit according to the circuit diagram and wiring table.
•
Test the circuit logic levels from front to back or back to front in an orderly manner for whatever
inputs give incorrect values. Use your full truth table created in your prelab to do this.
•
Document the errors found and the procedure you used to correct them.
When you have identified the problem(s), demonstrate the solution to the lab instructor. The lab instructor
must initial you results BEFORE you take you circuit apart or you will not get credit for the lab!
Once your circuit is working properly answer the following question, documenting your results in your lab
notebook.
What happens when the coded values (switch values) 1010, 1011, 1100, 1101, 1110, and 1111 are
input to the 7 SEGMENT DISPLAY? Why do you think this occurs?
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3
EE543 Introduction to Digital Systems
WIRING LIST
Wire +5 volts and ground to each chip (be careful not to connect to the wrong pins) and then complete this
wiring table to construct the circuit.
CHIP
Number
PIN
Number
S0
S1
S2
S3
TO
CHIP
Number
1
1
1
1
PIN
Number
2
1
4
13
3
4
3
4
1
2
3
1
2
1
3
1
4
10
1
4
4
10
1
2
5
4
9
1
12
12
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
3
3
3
4
5
6
6
8
11
2
2
2
2
2
1
3
6
8
9
2
2
2
5
2
10
C on 7 Seg display
3
3
3
3
3
3
3
4
6
6
8
11
3
5
3
9
A on 7 Seg Display
3
12
B on 7 Seg Display
4
4
4
4
4
1
3
6
11
12
4
2
4
5
3
13
D on 7 Seg Display
4
13
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1
EE543 Introduction to Digital Systems
1
2
1
3
9
S3
(MSB)
4
S2
5
10
1
1
6
2
1
8
12
13
2
3
5
4
1
11
2
6
12
13
10
9
2
1
1
S1
2
4
3
5
4
10
9
S0
(LSB)
4
5
3
3
3
4
6
13
12
3
3
11
2
8
D
(MSB)
C
11
B
8
A
(LSB)
6
EXCESS – 3 To BCD Converter
FIGURE 1
Last Update: 1/24/2020, 3:04 PM
4
Diagrams used in ECE 543 Labs
Pin Assignment Diagrams
The pin assignment diagrams show the IC, the internal logic gate connections and identifies the input
and output pins.
Fig.1 Pin Assignment diagram.
Logic Symbol or logic Gate Diagrams
A diagram showing the logic symbols, indicating the input and output pins.
Fig.2 Logic Symbol
Circuit Diagram
The circuit diagram shows how the circuit would be implemented in the lab. It shows the connection
between the logic switches(inputs) and the logic channel/logic monitor. It must also include connection
to VCC and Ground. S1 and S0 represent switches 1 and 0 respectively; LM0 represents channel 0 on the
logic monitor. Note that black wire is used for ground connections and red wires for VCC.
VCC
S1
S0
LM0
GND
Wiring diagram
the wiring diagram shows the actual connections of the logic switches(inputs), logic monitor(output) to
the logic symbol. It includes pin numbers and chip numbers. Pin numbers should correspond with the
pin assignment diagram. For example, pin 12 on the pin assignment diagram above is an input pin and
therefore can only be connected to a switch. The Chip numbers are used to identify the IC each gate
belongs to. For the diagram below, S1 and S0 represent switches 1 and 0 respectively; LM0 represents
channel 0 on the logic monitor. Note that the switches are connected to the same pins as the circuit
diagram above.
Pin numbers
S1
S0
1
2
Chip number
1
3
LM0
LABORATORY INSTRUCTIONS FOR ECE543 SPRING 2020
GENERAL
The purpose of the laboratory portion of this course is to acquaint the student with:
1. Experimental procedures and techniques as they apply specifically to digital systems.
2. Troubleshooting of digital circuitry when an incorrect output is observed.
3. The characteristics of the digital components and equipment that will be studied.
4. Methods of good record keeping.
LABORATORY PROCEDURE
1. The laboratory period is 2 hours long, and all required lab work must be completed during
this time.
2. Students will work independently.
3. Each student has the responsibility for coming to the laboratory fully prepared. This
preparatory work is to be documented in the form of a Preliminary Report (Prelab) and
is to be submitted to the lab instructor at a time designated in advance (see the Course
Syllabus for the dates that apply for your lab section). Satisfactory preparation is required
in order to be allowed to perform the experiment. A well-prepared student will be able to
proceed with the laboratory work without delay and with little, if any, assistance from the
laboratory instructors.
4. All equipment required will be available on the laboratory benches. YOU are responsible
for the proper use and care of this equipment. If you do not know how to use the equipment,
ASK the instructor! It is much better to ask than to receive a failing grade for the lab if the
equipment should be damaged due to your negligence. Whenever a student is responsible
for damage to laboratory instruments or equipment the student may be fined. Final
judgment regarding the assessment of these fines rests with the Instructor.
5. A burned-out fuse or IC chip is to be considered as evidence that something is seriously
wrong with the experiment and must be reported immediately to a laboratory instructor.
The instructor will approve the issuance of the proper replacement fuse or IC. A record
will be kept of the number of replacement fuses or ICs required for each student. If, at the
end of the semester, any student has more than a reasonable maximum number of fuses or
ICs, that student will be assessed the cost of the fuses or ICs in excess.
6. In very special cases, such as when there is a failure of the laboratory equipment or a student
is absent for legitimate medical reasons, arrangements can be made with the Instructor to
complete or make-up an experiment during designated make-up an experiment during
designated make-up laboratory periods during the semester.
7. The Laboratory Record of each student, whether completed or not, must be handed to the
laboratory instructor at the end of the laboratory period.
PRELIMINARY REPORT (PRE-LAB)
Each student is required to write a brief preparatory report on each experiment and turn it into the
instructor at the time designated. The Preliminary Report must be thorough enough to allow
another student or the instructor to perform the complete experiment using only the report and lab
instruction sheet.
The Preliminary Report should contain the following information:
1.
The date the prelab is to be handed in.
2.
Identification of the experiment by number and title.
3.
Your name.
4.
A brief yet informative statement defining the objective of the experiment.
5.
A table identifying the equipment required.
6.
Circuit diagram(s) and/or wiring diagram(s) showing the detail of the actual
connections to be used. Each piece of equipment or important component such as
switches, LED’s, chip, and pin numbers should be uniquely identified. When
variables such as X, Y, Z or C, B, A are used, they should be put down as well to
show what physical parts represent them. Where instructed, the appropriate Switch
and Logic channel labels should be used in your diagrams. A wiring table should
also be prepared for labs with more than one IC.
7.
Work done to complete the objective consisting of- a problem statement, truth
tables, state tables, state diagrams, Karnaugh maps, etc. The variables should be
identified by the same designations as those in the circuit and wiring diagrams so
that each piece of equipment or important component such as switches, LED’s, chip,
and pin numbers is uniquely identified.
8.
Predicted results that may be theoretically obtained before any experimental work
is actually performed in the lab should be put in this section. Any intermediate
results, such as those from between gates, should be included. Also answer here
any lab handout questions that ask for your predictions regarding the outcome of
the lab.
A well-prepared Preliminary Report will allow the student to proceed with the laboratory work
without delay and with little, if any, assistance from the laboratory instructors. Again, the purpose
of the Preliminary Report is to supply enough information so that another student or instructor
could perform the entire experiment.
LABORATORY RECORD
Each student is required to make a written record with a ‘Bic’ type ball-point pen (not felt-tip or
gel) of his/her work during the laboratory period. The laboratory record must be handed to the
laboratory instructor before the student leaves the lab. You MUST use a “Roaring Spring
Compositions” or equivalent, size 9¾” x 7½” commercial notebook with bound pages (DO NOT
buy a spiral notebook!). Such notebooks may be purchased at the bookstore. For each lab you
will be asked to staple your prelab into the notebook before beginning the experiment. Your
notebook will be in your possession only during your lab session. Notes should be made in the
record whenever they are needed to clarify or emphasize what was done and why.
The Laboratory Record should contain the following information:
1.
The date the laboratory work was performed.
2.
Identification of the experiment by number and title.
3.
Your name.
4.
A table identifying the equipment required.
5.
Circuit diagram(s) and/or wiring diagram(s) showing the detail of the actual
connections used . Each piece of equipment or important component such as
switches, LED’s, chip, and pin numbers should be uniquely identified. When
variables such as X, Y, Z or C, B, A are used, they should be put down as well to
show what phyiscal parts represent them.
6.
Original data, consisting of truth tables, timing diagrams, state tables, state
diagrams, etc. The variables should be identified by the same designations as those
in the circuit and wiring diagrams so that each piece of equipment or important
component such as switches, LED’s, chip, and pin numbers is uniquely identified.
When variables such as X, Y, Z or C, B, A are used, they should be put down as
well to show what phyiscal parts represent them. Any intermediate results, such as
those from between gates, should be included. Comparisons to the predicted results
should also go here.
7.
Your answers to any questions found within the lab handout.
8.
Your troubleshooting procedure (if required) and the changes it yielded as each
change was made.
9.
Notes on changes in procedure, difficulties encountered, and the method used to
overcome these difficulties.
10.
A discussion of the results.
11.
Conclusions and recommendations for further work.
The purpose of the Laboratory Record again is to supply sufficient information in order that a
student’s experimental work may be exactly duplicated so that all observations and data can be
verified.
Guidelines
The rules of Lab
Many people don’t know what prelab does. The job is to preview all the experiment
contents in advance. Its function is that I will use this prelab report to conduct laboratory
and I will follow prelab to complete the lab report in class. So prelab is a very important
report. You need to be very precise.
You need use Multisim to draw the circuit diagram. Like this,
You could search Multisim on Google:
“Please read instruction of laboratory
carefully!!!”
ECE 543: Introduction to Digital Systems
Instructor: Richard A. Messner, Ph.D.
Prelab #15: Half Adder Design
Prepared for
Alberta Ansah (TA)
Yue Liang (TA)
John Smith – ECE
Section 01
Department of Electrical and Computer Engineering
University of New Hampshire
January 21, 2020
Table of Contents
Introduction. ………………………………………………………………………………………………………. 3
Equipment Required. …………………………………………………………………………………………… 3
Procedures for Design. ………………………………………………………………………………………… 3
Truth Table, K-Maps, and Boolean Expressions. ……………………………………………………. 4
Testing Procedure ………………………………………………………………………………………………. 6
Wiring Diagram. ………………………………………………………………………………………………… 6
Predicted Results and Discussion. ……………………………………………………………………….. 7
References ………………………………………………………………………………………………………… 8
ECE 543
Prelab Report
2
Introduction
The objective of this experiment is to understand the construction and functionality of Half
Adder (HA) circuit using logic gates. In preparation for this lab, K-map , circuit design from
expression obtained from K-Map , wiring diagrams and predicted truth tables were created in
order to compare against actual lab results.
Equipment Required
Equipment
Quantity
Global Specialties Design and Prototyping PB-505
Wire Leads
7486
7408
Procedures for Design of Half Adder:
1
1
1
Block diagram:
HA is a combinational circuit that performs the addition of two bits. This HA circuit needs two
binary inputs and two binary outputs. The block diagram is shown in Fig.1 below.
Fig. 1 Block Diagram of Half Adder
Input
Output
A
B
Sum(S)
Carry (C)
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
1
Table1: Functional table
K-M ap
ECE 543
Prelab Report
3
Expression for Sum(S)
Expression for Carry(C)
S=A + B
S=A
C = AB
B
Logical Implementation of Half Adder circuit:
From the expression derived from the K-map for Sum and Carry of half adder, the design can be
logically implemented using two gates XOR and AND. The logical diagram is shown in Fig. 2
Fig. 2 Logical diagram of Half Adder
XOR and AND IC:
Texas Instruments Data Sheet and a diagram of the 7486 (XOR) and 7408 (AND) chip (Appendix
1) both demonstrate that the 7486 and 7408 IC contains 4 individual gates. Fig. 3 and Fig. 4
provides the relative location of these gates with respect to the pins. The functional table for XOR
and AND gate is shown in Table 2 and 3 respectively.
ECE 543
Prelab Report
4
Fig.3 Pin assignment diagram of 7486 IC
Fig. 4 Pin assignment diagram of 7486 IC
Input (A)
Input(B)
Output(Y)
0
0
0
0
1
1
1
0
1
1
1
0
Table 2.Truth table of XOR gate
Input (A)
Input(B)
Output(Y)
0
0
0
0
1
0
1
0
0
1
1
1
Table 3. Truth table of AND gate
Testing Procedure
1) Test the individual chip to verify its working using Logic monitor or logic probe .
2) Wire the circuit as per the complete circuit diagram and wiring list as shown in table 4.
3) After assembling the circuit, check for the functioning of design on logic monitor as per
the functional table shown in table 5.
4) If the circuit is not functioning as per the specification, troubleshooting the design by
checking each input and output pin for desired logic (either low (0) or high (1)) using logic
probe. Wiring List:
ECE 543
Prelab Report
5
Chip Pin TO Chip Pin
SW1
SW2
1
1
1
1
1
1
2
7
14
3
SW1
SW2
2
7
2
14
GND
+5V
LM0
2
1
2
2
GND
+5V
2
LM1
3
Table. 4 Wiring list
Input (Switches)
ECE 543
Output (Logic Monitor)
S1
S2
Chip 1, Pin3
0
0
1
1
0
1
0
1
0
1
1
0
Prelab Report
Chip 2, Pin
3
0
0
0
1
6
Table.5 Predicted State table
Fig.5 Wiring Diagram
Predicted Results and Discussion
Logic monitors predicted to register a logic level HIGH (red light) when a voltage of 2.2V
or greater is applied and a logic level LOW (green light) when a voltage of 0.8V or less is
applied. Voltage levels found in Global Specialties PB-505 manual. The predicted state table
for the design is shown in table 4.
References:
[1] Circuitstoday (2012) Retrieved August 26, 2014 from http://www.circuitstoday.com/half-adder
[1] Texas Instruments (1988) Retrieved August 26, 2014 from
http://www.alldatasheet.com/datasheet-pdf/pdf/27425/TI/SN7486.html
[2] Texas Instruments (1988) Retrieved August 26, 2014 from
http://www.alldatasheet.com/view.jsp?Searchword=SN7408
ECE 543
Prelab Report
7
ECE 543: Introduction to Digital System
Instructor: Richard A. Messner, Ph.D.
Prelab #4: INTRODUCTION TO INTEGRATED CIRCUITS AND DATA BOOKS
Fault Detection In Digital Logic
Prepared for
Alberta Ansah(TA)
YueLiang(TA)
Guankai Sang -CS
Section 04
Department of Electrical and Computer Engineering
University of New Hampshire
February 14, 2020
Table Of Contents
Introduction ……………………………………………………………………………………………………. 3
Equipment Required ……………………………………………………………………………………….. 3
Circuit Diagrams……………………………………………………………………………………………… 5
Writing Diagrams…………………………………………………………………………………………….. 6
Truth table………………………………………………………………………………………………………. 7
Prediction results ………………………………………………………………………………………….. 11
Conclusion & Recommendations …………………………………………………………………… 11
References ……………………………………………………………………………………………………. 11
Introduction
This laboratory is designed to challenge the student’s analytical skills and
practical knowledge of digital systems. Such detection and correction of faults is
commonly referred to as troubleshooting. At the completion of the lab you should have
the ability to find and correct faults or wiring errors in simple digital logic circuits. The
term BCD refers to representing the ten decimal digits in binary forms; which simply
means to count in binary. The Excess-3 system simply adds 3 to each number to make
the codes look different.
Equipment Required
EQUIPMENT
Global Specialties Design and Prototyping PB-
QUANTITY
1
505
Wire Leads
–
7400 TTL Integrated Circuit
4
Logic Probe
1
Table 1: Equipment required
Figure 1: 7400 TTL Integrated Circuit chips
Figure 2: EXCESS – 3 To BCD Converter
Circuit Diagrams
a. Our variables that will be used in each circuit will be in the following
configurations:
b. For our first circuit, 𝐸1 , the configuration will be the following:
c. For our second circuit, 𝐸2 , the configuration will be the following:
d. For our third circuit, 𝐸3 , the configuration will be the following:
e. For our fourth circuit, 𝐸4 , the configuration will be the following:
Binary Representation
Excess-3 Output
0000
0011
Table 2: Truth Table BCD to Excess-3
Final Circuit design
Figure 3: Final Circuit Design
Writing Diagrams
Wiring lists:
Truth table
Our BCD Excess-3 circuit will convert numbers from their binary representation to their
excess-3 representation as shown in the truth table in table 2.
Excess-3
MSB
LSB
Inputs
S3
S
2
S1
Chip #; Pin #
MSB
Outputs
Intermediates
S0
C1 C1 C4 C1 C2 C3 C4 C3 C1 C2
P3 P6 P3 P8 P3 P3 P6 P8 P11 P6
LSB
D
C B
A
0
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
0
0
1
0
1
1
0
0
0
0
1
0
1
1
0
1
1
1
0
0
1
1
0
1
0
0
1
1
1
1
1
1
0
0
0
0
0
1
0
0
1
0
1
1
0
1
1
1
1
1
0
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
0
1
1
0
0
1
1
0
1
1
1
0
0
0
1
1
1
1
1
1
0
0
1
0
0
1
0
0
0
1
1
1
0
0
0
1
1
1
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
0
1
1
0
1
0
1
0
1
1
0
1
0
0
1
0
1
1
0
1
1
1
1
0
1
1
0
1
0
1
1
1
1
1
0
1
1
0
0
0
1
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
0
1
1
1
0
1
1
0
1
1
0
1
0
1
0
1
1
0
1
0
1
1
1
0
1
0
0
1
0
1
1
0
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
0
0
Table 3: Truth Table BCD to Excess-3(With Intermediates)
𝒙𝟏
𝒙𝟐
0
𝒙𝟑
0
𝒙𝟒
0
𝒚𝟏
𝒚𝟐
0
𝒚𝟑
𝒚𝟒
0
1
1
1
0
0
0
0
0
0
1
0
0
0
1
0
0
1
0
1
0
0
1
1
0
1
1
0
0
1
0
0
0
1
1
1
0
1
0
1
1
0
0
0
0
1
1
0
1
0
0
1
0
1
1
1
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
1
1
1
0
0
Table 4: Truth Table BCD to Excess-3
Our task now is to use the truth table to find four switching expressions: one
for𝒚𝟏 , one for 𝒚𝟐 , one for 𝒚𝟑 , and one for 𝒚𝟒 .In the four K-maps that follow, the x’s are
referred to as “don’t care” terms. These don’t care terms are available because if you
look at the truth table in Table 3, no 𝒚𝟏 𝒚𝟐 𝒚𝟑 𝒚𝟒 valuations exist for 𝒙𝟏 𝒙𝟐 𝒙𝟑 𝒙𝟒 = 1010,
𝒙𝟏 𝒙𝟐 𝒙𝟑 𝒙𝟒 = 1011, 𝒙𝟏 𝒙𝟐 𝒙𝟑 𝒙𝟒 = 1100, 𝒙𝟏 𝒙𝟐 𝒙𝟑 𝒙𝟒 = 1101, 𝒙𝟏 𝒙𝟐 𝒙𝟑 𝒙𝟒 = 1110, and
𝒙𝟏 𝒙𝟐 𝒙𝟑 𝒙𝟒 = 1111. As such, we evaluate 𝒚𝟏 𝒚𝟐 𝒚𝟑 𝒚𝟒 = xxxx for each of these entries.
1. Karnaugh map for 𝒚𝟏 configuration
F(A,B,C,D) = A + BD + BC = A + B (D + C)
2. Karnaugh map for 𝒚𝟐 configuration
F(A,B,C,D) = BC’D’ + B’D + B’C = BC’D’ + B’D + B’C
3. Karnaugh map for 𝒚𝟑 configuration
CD
AB
00
01
11
00
1
1
01
1
1
11
X
10
1
X
10
X
X
X
X
11
10
F(A,B,C,D) = C’D’ + CD
4. Karnaugh map for 𝒚𝟒 configuration
CD
AB
00
01
00
1
1
01
1
1
11
X
10
1
X
X
X
X
X
F(A,B,C,D) = D’
To summarize, the following Boolean expressions will characterize our four
theoretical switching functions necessary to build the Excess-3 X circuit:
𝒚𝟏 = 𝐀 + 𝐁𝐃 + 𝐁𝐂
𝒚𝟐 = 𝐁𝐂’𝐃’ + 𝐁’𝐃 + 𝐁′𝐂
𝒚𝟑 = 𝐂’𝐃’ + 𝐂𝐃
𝒚𝟒 = 𝐃’
Prediction results
On our breadboard, we assigned our inputs to be DIO0, DIO1, DIO2, and DIO3, and we
assigned our outputs to be DIO4, DIO5, DIO6, and DIO7. After wiring the circuit, our
results proved that our circuit was correct and efficiently converted binary inputs into
excess-3 outputs.
Conclusion & Recommendations
In our lab, we created a circuit that converts binary coded inputs (8-4-2-1 code) into
excess-3 code. We began by creating a truth table where we converted from binary
coded inputs (x1, x2, x3, and x4) into excess-3 code (y1, y2, y3, and y4). We used this
truth table to find the minterm expansion for each output (in excess-3 code) y1, y2, y3,
and y4, and then simplified each minterm expansion with the use of karnaugh maps.
From here, we designed our circuit on paper and decided that it would be best to use 2
and-gates, 2 or-gates, and an inverter to create our circuit. Since we were using 5 gates
in total, we opted to use the breadboard as opposed to the NI DAQ.
References
M Morris Mano, professor of Engineering, California State University, Los Angeles
Math 645
Problem Set 3
Due Mar. 4, 2019
Drill Exercises While the problems are not required, it is in your best interest to use these
problems as practice problems. The majority of mistakes that occur on exams are algebra and
speed of finishing a test. Practice will greatly increase your understanding and success in this
course. Do not use a calculator or computational tool when practicing, as one will not be permitted
on the exam.
Text §2.1 #s 4-10, 17
Text §2.2 #s 1-9
Text §2.3 #s 11-16, 28
Text §2.5 #s 1-4, 7-8
Required Problems
1. (20 points) (a) Solve the equation, rAC = BC for A where A, B, C are all square matrices, r is
a nonzero scalar, and C is invertible.
(b) Suppose P and C are invertible and A = C −1 P BP −1 C. Solve for B in terms of A.
(c) Suppose A, B, C are n × n nonsingular matrices, and and r is a nonzero scalar. Does the equation, C(AB + rX)BA−1 = In have a solution, X? If so, find the solution.
(d) CHALLENGE Text §2.2 number 20
2. (20 points) Review the Invertible Matrix Theorem (Thm. 8 in §2.3) and then answer Text
§2.3 number 18. You should explain your reasoning and use a logical progression through Thm. 8
to answer this question. (For an example of a logical progression, we might start with knowing we
have a system that satisfies (d), then we can conclude that some other property, such as (e) is true,
which might then allow us to answer a related question.)
Note: I strongly recommend reviewing example problems and other problems in this section.
3. (30 points) For the following problems, you should go for convergence to at least 4 decimal
places of accuracy (C matrix and the d vector are on Canvas in the file Ps3no1.mat, so just load it
into matlab, but make sure you haven’t defined C or d beforehand. To load the file, simply type at
the matlab prompt >> load ps3no1.mat) Also, note that I expect you to use the iteration method
covered in class to approximate the inverse matrix and get the solution to converge to 4 decimal
places of accuracy.
(a) Text §2.6 number 13
(b) Using the above data, find the production levels needed to satisfy the following demand vector:
d~ = (98756, 83627, 17625, 12220, 76534, 5463, 9677)T
(c)Text §2.6 number 15
4. (30 points) Work out the following nasty-looking integral:
Z ∞
2
2
2
dx1 dx2 dx3 e−(x1 +4×1 x2 +4×1 x3 +7×2 +14×2 x3 +19×3 )
0
(see page 2)
To do this you should try to convert the integral to a form which allows you to calculate
the product of three integrals of the form
r
Z ∞
1 π
−a x2
dx e
=
2 a
0
No really, this is going to be fun…
(i) First, use an LDLT decomposition to find the quadratic form associated with the exponent.
Once this is done, you should have three squared terms in the exponent, (….)2 + (…)2 + (.)2 .
(ii) Now, redefine your coordinates so y1 is the first group in parentheses, y2 is the second group, and
y3 is the third. This defines a linear transformation between the x− and y−coordinates, T (x) = y.
(iii) The determinant of the matrix defining the transformation is the Jacobian, |J| of the transformation, so we can rewrite the integral as
Z ∞
2
2
2
dy1 dy2 dy3 |J| e−(α y1 +β y2 +γ y3 )
0
where you should find α, β, γ and the limits on the integral do not change since 0 and ∞ do not
change under the linear transformation.
(iv) Finally, use the gaussian integral formula to find the answer.