Vhdl for Synthesis

ELE591 - VHDL for Body Issue 1. 0: 1st December 2010 The point of this laboratory exemplification is to commonise you retrogression the principles of VHDL for body targeted at programmable logic shows. You conciliate respect how diversified VHDL names upshot in Register Transfer Raze (RTL) implementations and how these can be implemented retrogressionin biased logic shows. The principles of back-annotation conciliate to-boot be explored and how this can be used to perpend accomplishment limitations of biased hardware show mappings. This lab assumes you are already common retrogression Xilinx ISE and ModelSim, given that ELE335 is a prerequisite for this module. If inevitable, advise-retrogression the ELE335 lab pilot, which is intervening in the Coursework minority of the ELE591 module webpage. Most of the VHDL rasps needed for this lab are to-boot usageous from the identical precipitation. Exercise 1: Aim: To collate the upshots of divergent architectural names for the identical existence Steps: • Create a contrivance cunningated “exercise1”. Add the rasp ex1a. vhd as a “VHDL module” • Select the Spartan3 as the target show Compile and bodye the VHDL name and perpend the cunning news rasp, paying detail notice to the show utilisation epitome (and timing way resolution). To-boot perpend the RTL cunning. • Iterate retrogression the rasps ex1b. vhd and ex1c. vhd and collate the upshots. Exercise 2: Aim: To eluciage the use of “don’t care” values in body Steps: • Create a contrivance cunningated “exercise2”. Add the rasp docare. vhd as a “VHDL module” • Compile and bodye the cunning targeting the Spartan3 show • Add the rasp dontcare. hd as a “VHDL module” and iterate the body. • Collate the news rasps. Exercise 3: Aim: To eluciage logic show requirements for impeded versus mutually restricted input provisions Steps: • Create a contrivance cunningated “exercise3”. Add the rasp cond. vhd as a “VHDL module” • Compile and bodye the cunning targeting the Spartan3 show • Add the rasp exclusiv. vhd as a “VHDL module” and iterate the body. • Collate the news rasps. To-boot collate the timings at the cunning logic raze and at the situate and way raze. Exercise 4: Aim: To re-examination show and timing requirements of a involved reset exercise Steps: • Create a contrivance cunningated “exercise4”. Add the rasp cntpt. vhd as a “VHDL module” • Compile, bodye and impersonate the cunning targeting the Spartan3 show • Re-examination the news rasp paying detail notice to the reset equation. • Now perpend the rasp cntpt2. vhd which habituates a synchronous involved reset. • Attempt to impersonate the cunnings and dilate on the reset timing in twain subjects. Exercise 5: Aim: To collate CPLD and FPGA implementations of a FIFO cunning Steps: Create a contrivance cunningated “exercise5”. Add the rasp fifo. vhd as a “VHDL module” • Compile and bodye the cunning targeting the Spartan3 show • Recompile the cunning for a Coolrunner2. • Collate the news rasps and the upshoting RTL layouts. • Situate and way twain cunnings • Collate the cunning rasps paying detail notice to the climax detached quantity and the sum of shows used. Which timing parameter is the limiting ingredient on the detached quantity in each subject? Exercise 6: Aim: To eluciage the goods of implied remembrance Steps: • Create a contrivance cunningated “exercise6”. Add the rasp memcont. vhd as a “VHDL module” • Compile and bodye the cunning targeting the Spartan3 show. • Perpend the news rasp. • Add the rasp memcont2. vhd as a “VHDL module”. In this rasp the memorable specifyments for oe, we and addr are removed from inferior the reset qualification. • Compile and bodye the cunning targeting the Spartan3 show. • Collate the news rasp retrogression that of the former cunning. Verify that implied remembrance upshoted in the myth of a combinatorial latch. Exercise 7: Aim: To eluciage the usage of “one hot” encoding of abundant state-machines implemented in FPGA architectures Steps: • Create a contrivance cunningated “exercise7”. Add the rasp onehot. vhd as a “VHDL module” • Compile and bodye the cunning targeting the Spartan3 show • Situate and way the cunning and annals the sum of logic cells required, the setup duration, clock-to-output retrogression and climax detached quantity. • Now habituate the rasp notonehot. vhd. This uses the body cat's-paw to specify values to the diversified enumerated states. Compile and bodye the updated cunning targeting the Spartan3 show. • Situate and way the cunning and annals the sum of logic cells required, the setup duration, clock-to-output retrogression and climax detached quantity. • Collate the upshots retrogression the former cunning. This rotation of exemplifications should be written up as an INDIVIDUAL explicit lab news. The news conciliate be scant to a climax of 8 pages of deep passage (i. e. disregarding designation page etc). The hand-in age is the 17th December, unless you are certified differently.